FuryCore.ai
Company brief, October 2026
Proofs first, then silicon.
An AI computer on one chip, for training and inference. RISC-V cores run Linux and orchestrate FuryCore, an accelerator that puts the algorithms of modern AI models into silicon. Every block starts as a formal model; AI agents build against it, and proofs decide what ships.
Operators in silicon
Recurrence, expert routing, attention variants, sampling and audio front-ends get tiles of their own, next to a fast matmul and convolution array. Programmable compute runs the rest, so no model is locked out.
Formal first, AI-native
Each block starts as a formal model. AI agents write the hardware against it, and proofs gate every change before it merges.
An AI computer on one chip
RISC-V cores run Linux and real-time tasks and orchestrate the accelerator, for training and inference, from robots to on-prem racks.
What it trains and runs
Transformers and the simpler architectures before them: train and run them on one chip. Hardware support is a design target from day one; the labels show our software reference today.
- Language Reference runs today
- Vision Reference runs today
- Image and video generation Image: reference in progressVideo: next
- Speech and audio Reference in progress
- Decisions and encoders Embeddings: reference runs todayDecision models: next
- Robotics 3D mapping: reference runs todayVLA: next
- Classic and small models Next
- Training Reference trains small transformersHardware: design target
Formal first, AI-native
Agents write the hardware. Proofs decide what ships. Formal models are our specification, not an afterthought.
- Specify Each block starts as an executable model in Haskell, with the properties it must hold. AI drafts the model; people review it.
- Generate AI agents write the Clash hardware and the Rust runtime against that model.
- Gate A change that fails a gate does not merge.
- Measure FPGA performance counters feed the next design loop.
- Carry The same vendor-neutral cores move from FPGA to shuttle die to ASIC.
Prototyping on AWS F2
- Our Nix-packaged F2 pipeline runs end to end up to the hardware run: Spot-priced synthesis, AFI creation, and a NixOS F2 runner image.
- In simulation, the host software drives the live Clash gateware and streams real model weights through it.
| 0.6B bring-up model | f2.6xlarge |
| Most vision, speech and image-generation models, under 16 GB | f2.6xlarge |
| Gemma 4 26B-A4B, Qwen3.6-35B-A3B, quantized | f2.6xlarge to f2.12xlarge |
| Qwen3.8-27B, about 62 GB working set, and Qwen3.8-Flash-Next | f2.48xlarge |
| GLM-5.3 class, stretch goal | f2.48xlarge |
Where we are: TRL 2 to 3 today
| Clash design flow to working FPGA hardware | |
| Bit-exact testing against the software reference | |
| F2 platform | |
| AI agents implementing hardware | |
| Operator cores | |
| Formal specification and proof gate | |
| SoC: new RISC-V harts and integration | |
| Programmable compute and promotion loop | |
| Training tiles | |
| Silicon |
Filled: now. Outlined: next target. EU TRL scale, our own assessment.
Roadmap
- F2 hardware (TRL 4)
- SoC on an FPGA
- Partner workloads (TRL 5)
- Shuttle die (TRL 6)
- Product ASIC (TRL 7 and up)
Founding roles
Head of Formal Verification; Commercial co-founder, CEO; Silicon and ASIC; FPGA, RTL and SoC; ML systems. Co-founder or founding engineer, by fit. We write hardware in Haskell with Clash, software in Rust, and build everything with Nix. If types, proofs and reproducible builds belong in hardware design to you, talk to us.